JOP - Java Optimized Processor

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Documentation

This page is the starting point for various documents.

JOP User Manual

jop_short.pdf A two page paper about JOP.

An Introduction to the Design Flow for JOP

Getting Started, an introduction of build process.

SimpCon – a Simple SoC Interconnect, Draft

timing.pdf Bytecode instruction timing and microcode instruction set.

Further support is available via the Yahoo group java-processor .

Thesis

Paper

Martin Schoeberl, SimpCon - a Simple and Efficient SoC Interconnect,
In Proceedings of the 15th Austrian Workhop on Microelectronics, Austrochip 2007, Graz, Austria, October 2007. (pdf, bibtex).

Martin Schoeberl and Jan Vitek, Garbage collection for safety critical Java,
In Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems, JTRES 2007, Vienna, Austria, September 2007. (pdf, bibtex).

Christof Pitter and Martin Schoeberl, Towards a Java multiprocessor,
In Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems, JTRES 2007, Vienna, Austria, September 2007. (pdf, bibtex).

Martin Schoeberl, Architecture for object oriented programming languages,
In Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems, JTRES 2007, Vienna, Austria, September 2007. (pdf, bibtex).

Wolfgang Puffitsch and Martin Schoeberl, picoJava-II in an FPGA,
In Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems, JTRES 2007, Vienna, Austria, September 2007. (pdf, bibtex).

Martin Schoeberl. A Java processor architecture for embedded real-time systems,
Journal of Systems Architecture, doi:10.1016/j.sysarc.2007.06.001 , 2007. (pdf, bibtex).

M. Schoeberl, A Time-Triggered Network-on-Chip,
In International Conference on Field-Programmable Logic and its Applications , FPL 2007, Amsterdam, Netherlands, August, 2007. (pdf, bibtex).

C. Pitter and M. Schoeberl, Time Predictable CPU and DMA Shared Memory Access,
In International Conference on Field-Programmable Logic and its Applications , FPL 2007, Amsterdam, Netherlands, August, 2007. (pdf, bibtex).

R. Kirner and M. Schoeberl, Modeling the Function Cache for Worst-Case Execution Time Analysis,
In Proceedings of the 44rd Design Automation Conference , DAC 2007, San Diego, CA, USA, June 2007. (pdf, bibtex).

M. Schoeberl, Mission Modes for Safety Critical Java,
In 5th IFIP Workshop on Software Technologies for Future Embedded & Ubiquitous Systems , SEUS 2007, Santorini Island, Greece, May 2007. (pdf, bibtex).

M. Schoeberl, H. Sondergaard, B. Thomsen and A. P. Ravn, A Profile for Safety Critical Java,
In 10th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing , ISORC 2007, Santorini Island, Greece, May 2007. (pdf, bibtex).

M. Schoeberl and R. Pedersen, WCET Analysis for a Java Processor,
In Proceedings of the Workshop on Java Technologies for Real-Time and Embedded Systems , JTRES 2006, Paris, France, October 2006. (pdf, bibtex).

R. Pedersen and M. Schoeberl, Exact Roots for a Real-Time Garbage Collector,
In Proceedings of the Workshop on Java Technologies for Real-Time and Embedded Systems , JTRES 2006, Paris, France, October 2006. (pdf, bibtex).

R. Pedersen and M. Schoeberl, An Embedded Support Vector Machine,
In Proceedings of the Fourth Workshop on Intelligent Solutions in Embedded Systems , WISES 2006, Vienna, Austria, June 2006. (pdf, bibtex).

M. Schoeberl, Real-Time Garbage Collection for Java,
In Proceedings of the 9th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing , ISORC 2006, Gyeongju, Korea, April 2006. (pdf, bibtex).

M. Schoeberl, A Time Predictable Java Processor,
In Proceedings of the Design, Automation and Test in Europe Conference, DATE 2006, Munich, Germany, March 2006. (pdf, bibtex).

M. Schoeberl, Evaluation of a Java Processor,
In Tagungsband Austrochip 2005, Austrochip 2005, Vienna, Austria, October 2005. (pdf, bibtex).

M. Schoeberl, Design and Implementation of an Efficient Stack Machine,
In Proceedings of the 12th IEEE Reconfigurable Architecture Workshop, RAW 2005, Denver, Colorado, USA, April 2005. (pdf, bibtex).

F. Gruian, P. Andersson, K. Kuchcinski, and M. Schoeberl, Automatic Generation of Application-Specific Systems Based on a Micro-programmed Java Core,
In Proceedings of the 20th ACM Symposium on Applied Computing, Embedded Systems track, SAC 2005, Santa Fee, New Mexico, March 2005. (pdf, bibtex).

M. Schoeberl, A Time Predictable Instruction Cache for a Java Processor,
In Workshop on Java Technologies for Real-Time and Embedded Systems, JTRES 2004, LNCS 3292, Agia Napa, Cyprus, October 2004. (pdf, bibtex).

M. Schoeberl, Design Rationale of a Processor Architecture for Predictable Real-Time Execution of Java Programs,
In Proceedings of the 10th International Conference on Real-Time and Embedded Computing Systems and Applications, RTCSA 2004, Gothenburg, Sweden, August, 2004. (pdf, bibtex).

M. Schoeberl, Real-Time Scheduling on a Java Processor,
In Proceedings of the 10th International Conference on Real-Time and Embedded Computing Systems and Applications, RTCSA 2004, Gothenburg, Sweden, August, 2004. (pdf, bibtex).

M. Schoeberl, Java Technology in an FPGA,
In Proceedings of the International Conference on Field-Programmable Logic and its applications, FPL 2004, Antwerp, Belgium, August 2004. (pdf, bibtex).

M. Schoeberl, Restricitons of Java for Embedded Real-Time Systems,
In Proceedings of the 7th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing, ISORC 2004, Austria, Vienna, May 2004. (pdf, bibtex).

M. Schoeberl, JOP: A Java Optimized Processor,
In Workshop on Java Technologies for Real-Time and Embedded Systems, JTRES 2003, LNCS 2889, Catania, Italy, November 2003. (pdf, bibtex).

M. Schoeberl, Design Decisions for a Java Processor,
In Tagungsband Austrochip 2003, Linz, Austria, October 2003. (pdf, bibtex).

M. Schoeberl, Using a Java Optimized Processor in a Real World Application,
In Proceedings of the First Workshop on Intelligent Solutions in Embedded Systems, WISES 2003, Vienna, Austria, June 2003. (pdf, bibtex).

Working Paper

JOP

jop3_arch.ppt Power Point presentation of JOP.

FPGA

A small introduction to load a simple design to the Cyclone board can be found here: hello_world.pdf

tuning.pdf Tuning a Processor for FPGA Technology, describes how to squeeze out a few nano seconds for a higher clock frequency in JOP; now 100 MHz ;-)