JOP - Java Optimized Processor
This page contains the information you need to get a simulation of JOP running.
There are two ways to simulate JOP:
You can simulate JOP even with the free ModelSim XE III Starter Xilinx version.
Background InformationTo simulate JOP, or any other processor design, in a vendor neutral way models of the internal memories (block RAM) and the external main memory are necessary. Beside this, only a simple clock driver is necessary.
To speed-up the simulation a little bit a simulation of the uart output, which is used for
The following table lists the simulation files for JOP and which program generates the initialization data:
Following VHDL files have to be compiled in the following order:
simulation/sim_jop_types_100.vhd simulation/sim_ram.vhd simulation/sim_pll.vhd simulation/sim_jbc.vhd simulation/sim_rom.vhd simulation/sim_memory.vhd simulation/sim_uart.vhd jtbl.vhd bcfetbl.vhd offtbl.vhd core/cache.vhd core/mem32.vhd core/mul.vhd core/extension.vhd core/bcfetch.vhd core/fetch.vhd core/decode.vhd core/shift.vhd core/stack.vhd core/core.vhd io/cnt.vhd io/iomin.vhd top/jopcyc.vhd simulation/tb_jop.vhd
The actual version of JOP (at the usual download page) now contains all necessary file to run a simulation with ModelSim (or is there another VHDL simulator available?). In directory vhdl/simulation you will find:
In directory modelsim you will find a small batch file (
Step-by-step:Change to directory
jopsimHowever, this batch file uses the C-preprocessor of gcc to generate the correct JVM. If gcc is not installed on your system get Cygwin.
Change to directory
doit test test HelloAbort the download (
The final step is compiling the VHDL files with ModelSims
Comments?Drop me a note if you have troubles running the simulation, but also if it works fine for you: email@example.com
Copyright © 2000-2007, Martin Schoeberl