m255
13
cModel Technology
dD:\usr2\mlite\vhdl
Ealu
w1141610824
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Falu.vhd
l0
L16
Vgk@7XVB8o>:@8;1i5j1jf2
OX;C;6.0a;29
31
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Alogic
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work alu gk@7XVB8o>:@8;1i5j1jf2
l28
L24
VVJ;Zid[h7UbH<bSj]D7hE3
OX;C;6.0a;29
31
M2 ieee std_logic_1164
M1 work mlite_pack
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Ebus_mux
w1141610824
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Fbus_mux.vhd
l0
L22
VO@Gg0zlSmlM]BjJgRBzM]3
OX;C;6.0a;29
31
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Alogic
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work bus_mux O@Gg0zlSmlM]BjJgRBzM]3
l44
L43
V<?z`o8LEiO=QbQOnGQ<AP3
OX;C;6.0a;29
31
M2 ieee std_logic_1164
M1 work mlite_pack
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Econtrol
w1171479410
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Fcontrol.vhd
l0
L27
V6bA3g=T3JFHYb6WE0?VPO2
OX;C;6.0a;29
31
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Alogic
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work control 6bA3g=T3JFHYb6WE0?VPO2
l47
L46
V<1ZWjYMiP2I5m3Gn@XLRH0
OX;C;6.0a;29
31
M2 ieee std_logic_1164
M1 work mlite_pack
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Emem_ctrl
w1141610824
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Fmem_ctrl.vhd
l0
L17
Vn84gZ_o4??VL]8YAIc^RP3
OX;C;6.0a;29
31
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Alogic
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work mem_ctrl n84gZ_o4??VL]8YAIc^RP3
l47
L37
Vhe:W3U_hTl32Q6[hIKmn92
OX;C;6.0a;29
31
M2 ieee std_logic_1164
M1 work mlite_pack
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Emlite_cpu
w1171479448
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
Fmlite_cpu.vhd
l0
L75
VcCG^[ikPYgE_i?KVgM]_W1
OX;C;6.0a;29
31
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Alogic
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DE work mlite_cpu cCG^[ikPYgE_i?KVgM]_W1
l143
L92
VZWm28MPG[FoTj>EPI7O2N2
OX;C;6.0a;29
31
M4 work mlite_pack
M3 ieee std_logic_1164
M2 ieee std_logic_unsigned
M1 ieee std_logic_arith
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Pmlite_pack
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
w1171479368
Fmlite_pack.vhd
l0
L15
VV@P6c?>=ZRF_QZ7UHTEWl3
OX;C;6.0a;29
31
b1
M1 ieee std_logic_1164
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Bbody
DB work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
l0
L15
VV@P6c?>=ZRF_QZ7UHTEWl3
OX;C;6.0a;29
31
M1 ieee std_logic_1164
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
nbody
Emult
w1172960882
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Fmult.vhd
l0
L45
VD5_MjLNj@XML]AF7IOaTZ0
OX;C;6.0a;29
31
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Alogic
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work mult D5_MjLNj@XML]AF7IOaTZ0
l74
L55
V;z<`GVfSIEd=G<MG4AG[;0
OX;C;6.0a;29
31
M4 ieee std_logic_1164
M3 ieee std_logic_unsigned
M2 ieee std_logic_arith
M1 work mlite_pack
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Epc_next
w1141610824
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Fpc_next.vhd
l0
L16
V4X[Ta9m>foiiLe4?gn@DV0
OX;C;6.0a;29
31
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Alogic
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work pc_next 4X[Ta9m>foiiLe4?gn@DV0
l31
L29
VA7N@GamQC6WZFmLOFI5W01
OX;C;6.0a;29
31
M2 ieee std_logic_1164
M1 work mlite_pack
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Epipeline
w1141610824
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Fpipeline.vhd
l0
L18
Velml1?6n`7BVTI?;20V092
OX;C;6.0a;29
31
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Alogic
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work pipeline elml1?6n`7BVTI?;20V092
l54
L48
V1JFPaAKz@EDZL_62AamBS3
OX;C;6.0a;29
31
M2 ieee std_logic_1164
M1 work mlite_pack
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Eplasma
w1170035264
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Fplasma.vhd
l0
L37
VKY8HYAY`k>89IRRO73KG<2
OX;C;6.0a;29
31
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Alogic
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work plasma KY8HYAY`k>89IRRO73KG<2
l85
L56
VY>8ezVLI24P5^KdZdn`Ak0
OX;C;6.0a;29
31
M2 ieee std_logic_1164
M1 work mlite_pack
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Eplasma_if
w1170035264
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Fplasma_if.vhd
l0
L18
V>GfLm7DfbnZS^_za5?O;Q2
OX;C;6.0a;29
31
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Alogic
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work plasma_if >GfLm7DfbnZS^_za5?O;Q2
l69
L40
V`=81:SBW5PmYX:WZ5LRjZ2
OX;C;6.0a;29
31
M1 ieee std_logic_1164
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Eram
w1176833598
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP synopsys attributes 2Q8I4L@H0S1aHEXkjUYDC1
DP ieee std_logic_misc D2f;@P3IKJA9T^H8HI[9K0
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Fram.vhd
l0
L26
VoFIb[JmNcEXQ=ZZL5^;NK2
OX;C;6.0a;29
31
o-check_synthesis -93 -O0
tExplicit 1GenerateLoopIterationMax 100000
Alogic
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP synopsys attributes 2Q8I4L@H0S1aHEXkjUYDC1
DP ieee std_logic_misc D2f;@P3IKJA9T^H8HI[9K0
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work ram oFIb[JmNcEXQ=ZZL5^;NK2
l38
L36
V>F@8<QDAJfVa9V?@4A@`^2
OX;C;6.0a;29
31
M8 ieee std_logic_1164
M7 ieee std_logic_misc
M6 synopsys attributes
M5 ieee std_logic_arith
M4 ieee std_logic_unsigned
M3 ieee std_logic_textio
M2 std textio
M1 work mlite_pack
o-check_synthesis -93 -O0
tExplicit 1GenerateLoopIterationMax 100000
Ereg_bank
w1176833580
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Freg_bank.vhd
l0
L21
VFQYJ9Dd6b;9MXbUU=FN<o1
OX;C;6.0a;29
31
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Aram_block
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work reg_bank FQYJ9Dd6b;9MXbUU=FN<o1
l52
L42
V;a1W@XT59GS3mH3b_;G[[3
OX;C;6.0a;29
31
M4 ieee std_logic_1164
M3 ieee std_logic_unsigned
M2 ieee std_logic_arith
M1 work mlite_pack
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Eshifter
w1141610824
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Fshifter.vhd
l0
L17
V7cSWbMA1nKNFYdhNRTRB10
OX;C;6.0a;29
31
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Alogic
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work shifter 7cSWbMA1nKNFYdhNRTRB10
l34
L25
VBmcobig3Y>b0Yg4[^S^5F2
OX;C;6.0a;29
31
M2 ieee std_logic_1164
M1 work mlite_pack
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Etbench
w1141610824
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Ftbench.vhd
l0
L16
Vzib3mk=MOMH1gogz@:MHI1
OX;C;6.0a;29
31
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Alogic
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work tbench zib3mk=MOMH1gogz@:MHI1
l41
L19
VA^^[YAahlYjRbAJnD2PKK1
OX;C;6.0a;29
31
M2 ieee std_logic_1164
M1 work mlite_pack
o-check_synthesis -O0
tExplicit 1GenerateLoopIterationMax 100000
Euart
w1168725520
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP synopsys attributes 2Q8I4L@H0S1aHEXkjUYDC1
DP ieee std_logic_misc D2f;@P3IKJA9T^H8HI[9K0
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
Fuart.vhd
l0
L21
VTWJg^4R@Zb4EzDzS;bO3f1
OX;C;6.0a;29
31
o-check_synthesis -93 -O0
tExplicit 1GenerateLoopIterationMax 100000
Alogic
DP work mlite_pack V@P6c?>=ZRF_QZ7UHTEWl3
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP synopsys attributes 2Q8I4L@H0S1aHEXkjUYDC1
DP ieee std_logic_misc D2f;@P3IKJA9T^H8HI[9K0
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work uart TWJg^4R@Zb4EzDzS;bO3f1
l47
L35
VaE[_PHC;J`;o:gP;L7]?G1
OX;C;6.0a;29
31
M8 ieee std_logic_1164
M7 ieee std_logic_misc
M6 synopsys attributes
M5 ieee std_logic_arith
M4 ieee std_logic_textio
M3 std textio
M2 ieee std_logic_unsigned
M1 work mlite_pack
o-check_synthesis -93 -O0
tExplicit 1GenerateLoopIterationMax 100000
